ET1220 Lab 4.1 COMPLETE SOLUTION

Name:

Date:

Instructions:

Complete Parts 1, 2, and 3 of the attached Unit 4 Lab. As you complete these parts, answer the pertinent questions found in each corresponding section of this lab report. In some cases, you can transcribe data from the tables you already filled in during the lab experiment.

Part 1- Examine the Operation of the SR Latch

Theory:

1.      What is the state of Q out when S is logic high and R is low?

2.      Complete the following state table for an SR Latch.

Input

New

Output

S

R

State

Q

!Q

0

0

NC

1

0

Set

0

1

Reset

1

1

Illegal

Test Procedure:

3.      Record the observed values from Lab 4 Table 4-1. Record the values of the Q & !Q outputs, identify when the latch changes states and the status of the LEDs, on or off.

Input

New

Output

S

R

State

Q

!Q

Observations

1

0

0

0

0

1

0

0

1

0

0

0

0

1

0

0

1

1

4.      Paste a copy of the schematic you created, including your switches. Use Microsoft Paint to draw the connections.

Part 2- Examine the Operation of the JK Flip-Flop

Theory:

5.      How does a JK flip flop differ from an SR latch?

6.      If J & K are both logic high, and Q = 0, what will Q be equal to after the next clock pulse.?

7.      If J = 0 and K = 1, what will Q be equal to after the next clock cycle?

8.      Complete the following state table for the JK Flip-Flop. Enter the legal inputs, identify the state and the output.

Input

Output

J

K

State

Q

!Q

Planning:

9.      What are the pin numbers for VCC and Gnd on the 7476 Dual JK Flip-Flop?

10.   What happens if no clock signal is applied to the JK flip flop? Can the !pre & !clr inputs be used?

Test Procedure:

11.   Why not apply a sinewave to the JK clock input pin?

12.   Record the observed values from Lab 4 Table 4-2. Indicate the state of the flip-flops and LEDs as the Preset and Clear signals are enabled.

Initial Condition

!CLR set to 0

!CLR set to 1

!PRE set to 0

!PRE set to 1

Final Condition

Part 3- Use Registers to Data Transfer- Parallel to Serial to Parallel

Theory:

13.   What features of the 74195 Parallel-Access 4-bit Shift Register make it a useful data register?

14.   What feature of the 74125 Bus Buffer makes it useful as a buffer?

15.   Provide the truth table for the 74125 buffer.

!G

A

Y

16.   What is the application of a Tri-State buffer?

Planning:

17.   Describe the operation of the SH_!LD control input.

18.   Describe the operation of the Clear control input.

Test Procedure:

19.   List the steps of the data transfer procedure used to transfer data. What might happen if some steps are skipped?

20.   Record the observed values from Lab 4 Table 4-3. Indicate the state of the displayed data after each event.

Data In Display

Data Out Display

Dig Out

After

Load

After

Clock 1

After

Clock 2

After

Clock 3

After

Clock 4

After

Clock 1

After

Clock 2

After

Clock 3

After

Clock 4

Data In

Enable

Low

0001

0011

1100

1010

0101