ET1220 Lab 2.1 COMPLETE SOLUTION

ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 1 Part 1—Implement Part of a Seven-Segment Decoder Using AND-OR Logic Gates Theory: In lab 1 you used a 7447 BCD Decoder to drive a 7-segment display and you used individual gates to create a 2-bit adder. In this experiment you will explore the inner structure of the 7447 BCD decoder and the methods used to implement a digital logic solution. Individual gates will be used to drive segments “a” and “c” of the 7-segment display, truth tables and Boolean algebra will be used to develop the solution. Examine the diagram of the 7-segment display. Segment “a” will be illuminated for each of the following numbers: 0, 2, 3, 5, 6, 7, 8, & 9. Only the numbers 1 and 4 do not require segment “a”. Examine the truth table for segment “a”. DCBA “a” 0000 1 0001 0 0010 1 0011 1 0100 0 0101 1 0110 1 0111 1 1000 1 1001 1 1010 X 1011 X 1100 X 1101 X 1110 X 1111 X Where “a” equals 1 indicates that segment “a” should be illuminated. Where “a” equals 0 indicates that segment “a” should be dark. Where “a” equals X indicates a “don’t care” or invalid condition. Notice that 8 valid solutions exist. That would require numerous gates to implement. It will be easier to implement the 2 “NOT” solutions ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 2 Review the schematic diagram for the 7447 BCD decoder. Remember the 7447 sends a ground (0 or low) to turn on segments and sends 5V (1 or high) to turn off segments. This means that we should design our segment “a” gate circuit to turn off segment “a”. The circuit required to drive segment “a” should turn off segment “a” for numbers 1 and 4, otherwise segment “a” will be on or in an invalid, “don’t care” state. Segment “a” is turned off when +5V (1 or high) is applied to it. Examine the new truth table for segment “a”. Notice the don’t care conditions are no longer included, they don’t matter. DCBA “a” 0000 0 0001 1 0010 0 0011 0 0100 1 0101 0 0110 0 0111 0 1000 0 1001 0 Where “a” equals 1 indicates that segment “a” should be dark. Where “a” equals 0 indicates that segment “a” should be illuminated. Segment “a” will be turned off for numbers 1 and 4. The Boolean equation for this truth table is: ´ ´ ´ ´ ´ ´ By using the rules of Boolean algebra, the solution can be rearranged as follows. Take a moment and verify that the two solutions are identical. ´ ´ ´ ´ ´ ´ Examine the following gate structure and verify that it correctly reflects the Boolean solution. Notice that we can use three daul-input AND gates to create a 4-input AND gate. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 3  U7A, U7B and U6D implement the first term of the solution.  U7C, U7B and U7D implement the second term of the solution.  Both terms can share U7B because both terms of the solution contain ´ ´ . By using Boolean algebra, we can rearrange the terms. Now we repeat the process for segment “c”. Examine the diagram of the 7-segment display. Segment “c” will be illuminated for each of the following numbers: 0, 1, 3, 4, 5, 6, 7, 8, & 9. Only number 2 does not require segment “c”. Examine the truth table for segment “c”. DCBA “c” 0000 1 0001 1 0010 0 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 Where “c” equals 1 indicates that segment “a” should be illuminated. Where “c” equals 0 indicates that segment “a” should be dark. Where “c” equals X indicates a “don’t care” or invalid condition. Notice that 9 valid solutions exist. That would require numerous gates to implement. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 4 DCBA “c” 1001 1 1010 X 1011 X 1100 X 1101 X 1110 X 1111 X It will be easier to implement the 1 “NOT” solution. Remember the 7447 sends a ground (0 or low) to turn on segments and sends 5V (1 or high) to turn off segments. This means that we should design our segment “c” gate circuit to turn off segment “c”. The circuit required to drive segment “c” should turn off segment “c” for number 2, otherwise segment “c” will be on or in an invalid, “don’t care” state. Segment “c” is turned off when +5V (1 or high) is applied to it. Examine the new truth table for segment “a”. Notice the don’t care conditions are no longer included, they don’t matter. DCBA “c” 0000 0 0001 0 0010 1 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 Where “c” equals 1 indicates that segment “c” should be dark. Where “c” equals 0 indicates that segment “c” should be illuminated. Segment “c” will be turned off for number 2. The Boolean equation for this truth table is: ´ ´ ´ ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 5 Examine the following gate structure and verify that it correctly reflects the Boolean solution. Notice that we can use three dual-input AND gates to create a single 4-input AND gate. Examine the entire gate structure required to implement a solution to drive segments “a” and “c” are as follows. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 6 This requires 13 gates to implement, that is a lot of gates and connections. Several methods are available to reduce or simplify Boolean solutions. Karnaugh mapping and software applications can further reduce the number of gates. Examine the Boolean expressions for both solutions. ´ ´ ´ ´ ´ ´ ´ ´ ´ By inspection we can determine the solution for segment “c” cannot be reduced. However, the solution for segment “a” has values that are shared in each of the terms. By applying the rules of Boolean algebra, solution “a” can be rearranged. ´ ´ ( ´ ´) Notice the ORed expression. Let’s examine its truth table. The output is only true when A & C are different values. The truth table is that of an XOR gate, we can replace the ORed term with an XOR gate CA “c” 00 0 01 1 10 1 11 0 The simplified solution is represented by the following expression and gate structure. ´ ´ ( ) The entire solution now has 10 gates, a 30% reduction in complexity! ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 7 Planning: 1. Examine the block diagram in figure 2-1. This is the circuit will work identically to the circuit Lab 1 Part 1. Figure 2-1  The circuit is comprised of the myDAQ, the circuit from Lab 1 and the new circuit to drive segments “a” and “c”. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 8  Input to the circuit comes from the myDAQ, data lines 0 thru 3. The circuit inputs are applied to the 7447 inputs (ABCD) and the new circuit inputs (ABCD).  The 7447 inputs (ABCD) will be decoded and will change the outputs to drive the correct segments (b, d, e, f & g). Notice the 7447 is no longer connected to segments “a” &”c”.  The new circuit inputs will be decoded and will change the outputs to drive the correct segments (a & c).  Although the current limited resistors are not show, they are part of the circuit. 2. Familiarize yourself with the following schematic diagram of the circuit, figure 2-2. Notice the 7447 output “a” and “c” are no longer connected to the 7-segment display segments “a” & “c”. Figure 2-2  Outputs from the myDAQ data lines 0 thru 3 are connected to inputs ABCD of the 7447 BCD decoder and to inputs ABCD of the new circuit that drives segments “a” and “c”. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 9  Notice the arrangement of the inverters. This is a common method of connecting decoders to input line, it provides both the input signal and it’s NOT (or inverted) value. For example, input A is connected to the XOR gate (7486) U7A and the NOT gate (7404) U5A. U5A provides ´ to the AND gate (7408) U6B.  The outputs “a” and “c” of the new circuit are now connected to the current limiting resistors and will control segments “a” and “c” of the 7-segment display segments.  Remember, the resistors are required, they will limit the current to the LED. If the resistors are not used, the LED will be damaged! ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 10 Examine the pin descriptions of the new circuit components, figure 2-3. Figure 2-3  Notice that the VCC (5V) and GND (ground reference) lines are at the upper right and lower left, respectively, on each gate. And the gate pin locations are the same for each IC.  From the schematic you can determine that five of the AND (in 2 chips), one of the XOR and four of the NOT gates will be used. 3. Examine the wiring diagram for the gate structure, figure 2-4. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 11 Figure 2-4 4. Use Images 1 and 2 from the ET1220 Lab 2 Image Powerpoint to complete your wiring plan.  Image 1 is the complete, comprehensive schematic for the entire circuit.  Image 2 shows the schematic for the new circuit and the wiring pin out diagram for the ICs  Use Image 1 & 2 to complete the wiring diagram.  Be prepared to include your completed wiring diagram with the lab report document. Preparation: 1. Locate the following items from your lab equipment: • myDAQ • Protoboard with previously built 7447 7-Segment Display circuit • Logic Probe • Datasheet for the following ICs (Appendix A of the Lab Manual, or an Internet search) o 74LS08 AND o 74LS86 XOR o 74LS04 NOT 2. Use the correct ESD procedures. • Make sure to wear the ESD wrist strap and make sure that it is connected to the MyDAQ ground. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 12 3. Before attempting to make changes to the existing circuit, verify that the circuit from lab 1 operate correctly. Use the lab and lab images from lab 1 to verify the circuit. Review steps 5, 6 & 7 from Lab 1’s Clean Up procedure (at the end of the lab). 4. Obtain and organize the following components from your kit, they should be on one of the two ESD foam pads. Place them on the circuit board, but do not insert them. • Two 74LS08 AND ICs • One 74LS86 XOR IC • One 74LS04 NOT (inverter) IC Wiring Procedure: 1. Insert the chips into the protoboard, remember the notches or pin 1 markings need to be at the top. Spread the chips out a bit to provide room for wiring. • Examine Image 3 from the ET1220 Lab 2 Image Powerpoint to chip placement 2. Disconnect the myDAQ Test Interface from your circuit, you will reconnect it when you have finished. 3. You should now be ready to wire you circuit. • Remember to cut wires that are not too long or two short, make sure that your leads are not stripped too long or too short. • Successfully wiring the circuit will require close attention to detail. • Make sure that power is not supplied to the circuit until finished. • Provide a power and ground connection for each chip. • Compare your wiring diagram with Image 4 from the ET1220 Lab 2 Image Powerpoint to verify that your diagram is correct. Make any required corrections. 4. Use your wiring diagram to wire the circuit. 5. Once you have finished wiring, use Images 5 through 11 of the ET1220 Lab 2 Image Powerpoint to verify that the circuit is wired correctly.  Remember to disconnect the 7447 segment “a” and “c” outputs from the current limiting resistor. 7447-pins 13 & 11. The wires from the new circuit will replace those wires. 6. The final step will be to connect the myDAQ Test Interface to the circuit. • Data switch 0 through 3 will be connected to inputs ABCD of the 7447 BCD Decoder and inputs ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 13 ABCD of the new circuit. o Data line 0 (A) is connected to 7447-pin 7 and to the 7404 and the 7486 per your wiring plan. o Data line 1 (B) is connected to 7447-pin 1 and to the 7404 and the 7408 per your wiring plan. o Data line 2 (C) is connected to 7447-pin 2 and to the 7404 and the 7486 per your wiring plan. o Data line 3 (D) is connected to 7447-pin 6 and to the 7404 per your wiring plan. 7. Before connecting the MyDAQ to the USB and applying power, verify that all chips have their notch (or pin 1 marking) at the top and that 5V connected to the upper right pin and ground is connected to the lower left pin. Test Procedure: 1. Apply power to the circuit by connecting the MyDAQ USB cable. 2. Start the NI ELVISmx Instrument Launcher  Select the DigOut Instrument, make sure all data lines are set to 0, star the instrument by selecting Run. 3. If you correctly wired the circuit, the 7-seven display should display a 0 (zero).  If a zero is not displayed, you will need to follow the troubleshooting procedure before proceeding. 4. Toggle the Line data switches in the following order. Remember down is a low and up is a high.  The 7447 is a BCD (binary coded decimal) decoder, it will only provide valid outputs for 0 through 9. Values of A (10) through F (15) will provide non numeric symbols.  Complete the following table. Also see the ET1220 Lab 2 Report Document.  If the 7-segment displays the numbers 0 through 9, you have wired the circuit correctly! ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 14 Inputs Output Binary Data Lines BCD Number Seven Segment Display 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Table 2-1 5. You should now be able to:  Create a true Boolean expression based upon a truth table.  Build a decoder circuit using logic gates.  Use Boolean rules to simplify a Boolean expression. 6. Remove power from the circuit by disconnecting the myDAQ’s USB cable from the computer. Clean Up: 1. Do not disassemble the 7447 BCD Decoder and 7-Segment display circuit, it will be used in the next lab. 2. Remove the new circuit from the protoboard.  Use proper ESD procedures.  Carefully remove the wires connected to the following ICs.  Both 74LS08 AND ICs  74LS04 NOT IC  74LS86 XOR IC  Carefully remove these ICs. Be very careful to remove them from the ICs without bending their ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 15 pins.  Store the ICs by placing them back on the ESD proof foam pads from which they were removed. 3. Reconnect outputs “a” and “c” from the 7447 BCD Decoder to the resistor connected to segments “a” and “c” of the 7-segment display.  “a”: 7447-pin 13  “c”: 7447-pin 11 4. Reconnect the myDAQ to inputs ABCD of the 7447 (pins 7, 1, 2 & 6) per the wiring diagram, Image 6 of the ET1220 Lab 1 Image Powerpoint.  Use Image 8 of the ET1220 Lab 1 Image Powerpoint to verify the connections.  The only change to the 7447 BCD Decoder/7-Segment display circuit were to the 7447 inputs ABCD. Verify that the myDAQ is connected to the correct pins, verify that the ground wire is removed from the 7447 pin 6. 5. After verifying that the circuit is wired correctly, apply power to the circuit by connecting the MyDAQ USB cable. 6. Verify the 7-segment display circuit operates correctly.  If it doesn’t operate correctly, check the inputs to the 7447. 7. Remove power to the circuit by disconnecting the MyDAQ USB cable. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 16 Part 2—Process Control using Combinational Logic Theory: In this experiment you will examine a method used to implement a process control solution using combinational logic. Examine figure 2-5, this represents a process control system. To the left is a tank, to the right is the control circuit used to control a process. • The purpose of the tank is to provide a reservoir of fluid that is always available. The tank should never be allowed to become empty, nor should it be allowed to become completely full. • The outlet valve provides fluid to the next stage in the process, the rate that the next stage uses the fluid is not constant, thus the flow increases and decreases. Hence the level in the process tank will rise and fall as well. • The inlet valve is connected to the source of the fluid. As the process tank empties, the inlet valve will allow the tank to refill. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 17 The following steps represent a standard process used to implement combinational logic solutions. Step 1- Understand how the actuators and sensors operate. These valves and sensors operate as follows: • The valves operate identically, 5V (or a high) will open the valve and allow fluid to flow. Absence of 5V (or a low) will shut the valve and stop fluid flow. • The fluid sensors operate identically, if fluid level is at or above the sensor, it sends a 5V (or high) signal that indicates that fluid is sensed. If the fluid level is below the sensor, it sends a 0V (or low) signal that indicates that fluid is not sensed. Step 2- Identify the process control requirements. This process control requirements are as follows: • If the top fluid sensor detects fluid, the inlet valve must shut (stop filling the tank) and the outlet valve must open (allow fluid to leave the tank). • If the bottom fluid sensor detects fluid, the outlet valve must be open (allow fluid to leave the tank). • If the bottom fluid sensor does not detect fluid, the outlet valve must be shut (stop fluid from leaving the tank). • If the top fluid sensor detects fluid, but the bottom fluid sensor doesn’t detect fluid, an error exists. Both valves must be shut and a warning signal must be triggered. Step 3- Identify control system inputs and outputs, assign signal names that indicate the purpose of the system. This control system has two inputs and three outputs. • Inputs- Two sensors are available, each has two possible outputs. o FT is the signal that represents the state of the top fluid sensor. FT = 0, fluid is not detected FT = 1, fluid is detected o FB is the signal that represents the state of the bottom fluid sensor. FB = 0, fluid is not detected FB = 1, fluid is detected • Outputs- Two valves are available, each has two possible states. The error indicator has two possible states. • Fin is the signal that represents the state of the inlet valve. Fin = 0, valve is shut, no fluid enters the tank Fin = 1, valve is open, fluid enters the tank • Fout is the signal that represents the state of the outlet valve. Fout = 0, valve is shut, no fluid leaves the tank Fout = 1, valve is open, fluid leaves the tank • Er is the signal that represents the tank's error state. Er = 0, no error detected ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 18 Er = 1, error detected Step 4- Create a truth table based that represents the states of the sensors and actuators. Examine the truth table for the process. Inputs Outputs FT FB Fin Fout Er Description 0 0 1 0 0 Tank is empty, open inlet, shut outlet 0 1 1 1 0 Tank is good, open inlet, open outlet 1 0 0 0 1 Error- fluid detected at the top, but not bottom! Shut valves 1 1 0 1 0 Tank is full, shut inlet, open outlet • Notice that four input state combinations exist. For each possible combination of input states, each output will either be true or false. Output Fin has two true conditions, Fout has two true conditions, and Er has one true condition. Step 5- Create Boolean expressions based upon the truth table. Each true output will have a Boolean term in an expression. Examine the Boolean expression for each of the output signals. ´ ´ ´ ´ ´ Step 6- Use Boolean algebra, Karnaugh mapping or some other method to minimize the number of gates required to implement the solution. For now, details of this optimization process will be skipped. Step 7- Create the gate structure based upon the minimized Boolean expression. Examine the following gate structures. • These gate's logic diagram implement the process control solution. Planning: 1. Review the block diagram for the process control circuit. ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 19  Remember that each sensor will provide 5V if fluid is detected and 0V is fluid is not detected. 5V will open the valve and allow fluid to flow. An error indicator will illuminate during illegal conditions. 2. Examine the Multisim implementation of the process control system. • Compare the block diagram to the schematic. The sensors, actuators and signal names are identified on both diagrams. • The valves are represented by green LEDs, the error lamp is represented by a red LED. An illuminated LED represents a closed valve (fluid flows). • The sensors are represented by SPDT switches. When the switch is in the down position it ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 20 represents the absence of fluid and 0V is applied to the control circuit. When the switch is in the up position, it represents the detection of fluid and applies 5V to the control circuit. Preparation: 1. Open MultiSim and open the ET1220.U2.Lab 2 Part 2 file. 2. Press F5 to start the simulation. 3. Use your mouse to select one of the two switches that represents the fluid sensor, either the top or the bottom sensor.  Toggle the switch by left-clicking on it or press the key associated with the switch.  For example, 4. Toggle the switches and make sure the LEDs turn on and off. Test Procedure: 1. Systematically change the sensor toggle switches following the order of table 2-2. For example, for the first test, make sure both switches are down.  For each input state, identify whether fluid is detected or not detected by each sensor Inputs Fluid Detected- True or False FT FB FT FB 0 0 0 1 1 0 1 1 Table 2-2 s ET1220: Module 2 Logic Expressions and Boolean Algebra Lab 2.1 Lab Procedure 21 2. For each input state, identify the condition of the valve or light. Inputs Outputs- On or Off FT FB Fin Fout Er 0 0 0 1 1 0 1 1 Table 2-3 3. Review the following Boolean expressions that represent the gate logic. ´ ´ ´ ´ ´ • Two of the terms can be reduced. Use Boolean algebra to reduce the terms. Use the Microsoft Word equation editor to show your work. Your result will be submitted with your lab report. 4. Modify the Multisim file using your logic solution. Test your solution and prove that your solution operates identically to the original solution. 5. Save a copy of your solution. 6. Use the PrintScreen function to obtain a copy of your circuit. You will need to submit your modified circuit with your lab report. 7. You should now be able to:  Create a truth table based upon a Boolean expression.  Use Boolean algebra to simplify a Boolean expression.  Read a process control diagram.  Modify an existing process.  Use Multisim to simulate process control systems.