ET1220 Lab 3.1 COMPLETE SOLUTION

Name:

Date:

Instructions:

Complete Parts 1, 2, and 3 of the attached Unit 3 Lab. As you complete these parts, answer the pertinent questions found in each corresponding section of this lab report.  In some cases, you can transcribe data from the tables you already filled in during the lab experiment.

Part 1- Convert Hexadecimal to BCD using Standard Logic Devices

Theory:

1.      Convert the following hexadecimal numbers into their BCD equivalent.  Show your work.

a.      Fh 

b.      Ah 

c.      7h             

d.      10h           

2.      What is the purpose the 7483 C0 input?

Planning:

3.      What is the purpose of the LED in Figure 3-1?

4.      Why is the 7485 Magnitude Comparator’s A=B input connected to a logic high and the A<B & A>B inputs tied to logic low during this experiment?

Wiring Procedure:

5.      Why is it important to number all of the chip pins in your diagrams before commencing with wiring?

6.      What is the purpose of the 330 Ohm and 1k Ohm resistors?

Test Procedure:

7.      Record the observed values from Lab 3 Table 3-1.  Indicate the BCD number displayed, the status of the LED and the 7-Segment display.

Inputs

Output

Binary

Data Lines

Equiv BCD Number

Carry

LED

Seven Segment Display

3

2

1

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

Part 2- Process Control using Standard Logic

Theory:

8.      Provide a basic explanation that describes how a simple demultiplexer/decoder works.

9.      For the decoder below, which output is low when A1A0 = 11?  When A1A0 = 10?

Planning:

10.   What feature of the Dual 1-of-4 Decoder/Demultiplexer requires that the actuators’ (valves and LED) polarities must be reversed?

11.   The combinational logic solution to the process control problem used an OR gate to provide the true outputs to valves.  The OR gate provides a high output when any input is high.  What was used to replace the OR gate so that any true low output is applied properly to the valves (Fin & Fout)?

Test Procedure:

12.   Record the observed values from Lab 3 Table 3-2.  Indicate whether fluid is detected or not detected, (yes or no).

Inputs

Fluid Detected- True or False

FT

FB

FT

FB

0

0

0

1

1

0

1

1

13.   Record the observed values from Lab 3 Table 3-3.  Indicate the condition of the valve or LED (on or off).

Inputs

Outputs- On or Off

FT

FB

Fin

Fout

Er

0

0

0

1

1

0

1

1

14.   Record the observed values from Lab 3 Table 3-4.  Describe the results of the LEDs in the Description column.

Inputs

Outputs

Input

State

Fin

Fout

Er

Description

00

0

1

0

0

01

1

1

1

0

10

2

0

0

1

11

3

0

1

0

15.   Paste (or attach) a PrintScreen copy of your working schematic here.

Part 3- Implement a Parity Generator using Standard Logic

Theory:

16.   In the table below, indicate the correct parity bit to indicate odd parity and the new data.

Data

Bits

Odd

Parity Bit

New

Data

1000

1001

1010

1011

1100

1101

1110

1111

17.   For the 74151, which channel will be routed to output Y when the addresses ABC =  "110"?

Planning:

18.   Describe the process you used to determine how to connect D0 or  not D0 to the 74151 D0-D7 inputs inputs. 

Test Procedure:

19.   Record the observed values from Lab 3 Table 3-6.  For each nibble of data, identify the Even Parity bit and the LED status.

Data

Bits

Even

Parity Bit

LED On or Off

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20.   Paste (or attach) a PrintScreen copy of your working MultiSim schematic here.