TEST BANK FOR The Microprocessors Programming, Interfacing, Software 4th By Walter A. Triebel

1 Introduction to Microprocessors and Microcomputers 4
2 Software Architecture of the 8088 and 8086 Microprocessors 5
3 Assembly Language Programming 9
4 Machine Language Coding and the DEBUG Software Development 11
Program of the PC
5 8088/8086 Programming—Integer Instructions and Computations 16
6 8088/8086 Programming—Control Flow Instructions and Program 23
Structures
7 Assembly Language Program Development with MASM 33
8 The 8088 and 8086 Microprocessors and their Memory 35
and Input/Output Interfaces
9 Memory Devices, Circuits, and Subsystem Design 42
10 Input/Output Interface Circuits and LSI Peripheral Devices 49
11 Interrupt Interface of the 8088 and 8086 Microprocessors 55
12 Hardware of the Original IBM PC Microcomputer 58
13 PC Bus Interfacing, Circuit Construction, Testing, and 63
Troubleshooting
14 Real-Mode Software and Hardware Architecture of the 80286 68
Microprocessor
15 The 80386, 80486, and PentiumR Processor Families: Software 71
Architecture
16 The 80386, 80486, and PentiumR Processor Families: Hardware 77
Architecture
CHAPTER 1
Section 1.1
1. Original IBM PC.
2. A system whose functionality expands by simply adding special function boards.
3. I/O channel.
4. Personal computer advanced technology.
5. Industry standard architecture.
6. Peripheral component interface (PCI) bus
7. A reprogrammable microcomputer is a general-purpose computer designed to run
programs for a wide variety of applications, for instance, accounting, word processing,
and languages such as BASIC.
8. Mainframe computer, minicomputer, and microcomputer.
9. The microcomputer is similar to the minicomputer in that it is designed to perform
general-purpose data processing; however, it is smaller in size, has reduced capabilities,
and cost less than a minicomputer.
10. Very large scale integration.
Section 1.2
11. Input unit, output unit, microprocessing unit, and memory unit.
12. Microprocessing unit (MPU).
13. 16-bit.
14. Keyboard; mouse and scanner.
15. Monitor and printer.
16. Primary storage and secondary storage memory.
17. 360K bytes; 10M bytes.
18. Read-only memory (ROM) and random access read/write memory (RAM).
19. 48K bytes; 256K bytes.
20. The Windows98R program is loaded from the hard disk into RAM and then run. Since
RAM is volatile, the operating system is lost whenever power is turned off.
Section 1.3
21. 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit.
22. 4004, 8008, 8086, 80386DX.
23. 8086, 8088, 80186, 80188, 80286.
24. Million instructions per second.
25. 27 MIPS
26. Drystone program.
27. 39; 49.
28. 30,000, 140,000, 275,000, 1,200,000, 3,000,000.
29. A special purpose microcomputer that performs a dedicated control function.
30. Event controller and data controller.
31. A multichip microcomputer is constructed from separate MPU, memory, and I/O
ICs. On the other hand, in a single chip microcomputer, the MPU, memory, and I/O
functions are all integrated into one IC.
32. 8088, 8086, 80286, 80386DX, 80486DX, and PentiumR processor.
33. Real mode and protected mode.
34. Upward software compatible means that programs written for the 8088 or 8086 will
run directly on the 80286, 80386DX, and 80486DX.
35. Memory management, protection, and multitasking.
36. Floppy disk controller, communication controller, and local area network controller.
Section 1.4
37. MSB and LSB.
38. 2-2 = 1/4
39. 1 and 2+5 = 1610; 1 and 2-4 = 1/16
40. (a) 610, (b) 2110, (c) 12710.
41. Min = 000000002 = 010, Max = 111111112 = 25510.
42. (a) 000010012, (b) 001010102, (c) 011001002
43. 00000001111101002
44. (a) .12 (b) .012 (c) .010112
45. C and 16+2 = 25610
46. 16+4 = 65,53610
47. (a) 39H, (b) E2H, (c) 03A0H.
48. (a) 011010112, (b) 111100112, (c) 00000010101100002.
49. C6H, 19810.
50. MSB = 1, LSB = 0.
51. 8005AH, 1,048,66610.
CHAPTER 2
Section 2.1
1. Bus interface unit and execution unit.
2. BIU.
3. 20 bits; 16 bits.
4. 4 bytes; 6 bytes.
5. General-purpose registers, temporary operand registers, arithmetic logic unit (ALU),
and status and control flags.
Section 2.2
6. Aid to the assembly language programmer for understanding a microprocessor's
software operation.
7. There purpose, function, operating capabilities, and limitations.
8. 14
9. 1,048,576 (1M) bytes.
10. 65,536 (64K) bytes.
Section 2.3
11. FFFFF16 and 0000016.
12. Bytes.
13. 00FF16; aligned word.
14. 4433221116; misaligned double word.
15. Address Contents
0A003H CDH
0A004H ABH
aligned word.
16. Address Contents
0A001H 78H
0A002H 56H
0A003H 34H
0A004H 12H
misaligned double word.
Section 2.4
17. Unsigned integer, signed integer, unpacked BCD, packed BCD, and ASCII.
18. (a) 7FH
(b) F6H
(c) 80H
(d) 01F4H
19. (0A000H) = F4H
(0A001H) = 01H
20. -1000 = 2's complement of 1000
= FC18H
21. (a) 00000010, 00001001; 00101001
(b) 00001000, 00001000; 10001000
22. (0B000H) = 09H
(0B001H) = 02H
23. NEXT I
24. (0C000H) = 34H
(0C001H) = 33H
(0C002H) = 32H
(0C003H) = 31H
Section 2.5
25. 64Kbytes.
26. Code segment (CS) register, stack segment (SS) register, data segment (DS) register,
and extra segment (ES) register.
27. CS.
28. Up to 256Kbytes.
29. Up to 128Kbytes.
Section 2.6
30. Pointers to interrupt service routines.
31. 8016 through FFFEF16.
32. Instructions of the program can be stored anywhere in the general-use part of the
memory address space.
33. Control transfer to the reset power-up initialization software routine.
Section 2.7
34. The instruction pointer is the offset address of the next instruction to be fetched by
the 8088 relative to the current value in CS.
35. The instruction is fetched from memory; decoded within the 8088; operands are read
from memory or internal registers; the operation specified by the instruction is performed
on the data; and results are written back to either memory or an internal register.
36. IP is incremented such that it points to the next sequential word of instruction code.
Section 2.8
37. Accumulator (A) register, base (B) register, count (C) register, and data (D) register.
38. With a postscript X to form AX, BX, CX, and DX.
39. DH and DL.
40. Count for string operations and count for loop operations.
Section 2.9
41. Offset address of a memory location relative to a segment base address.
42. Base pointer (BP) and stack pointer (SP).
43. SS
44. DS
45. Source index register; destination index register.
46. The address in SI is the offset to a source operand and DI contains the offset to a
destination operand.
Section 2.10
47. Flag Type
CF Status
PF Status
AF Status
ZF Status
SF Status
OF Status